DATRON 1061A PDF

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LAgCb I B z res c. To compensate for the current gain drift of Q12 approx. During the time that the SIG line is at logic-1 Mthe primary counter in M23 is enabled and counts out the signal period 20ms in normal mode, or 2. A complete program listing for the same calibration operation assuming an HP controller is as datrno Access to the non-volatile memory is gained using a key inserted into the rear panel.

Delivery times may vary, especially during peak periods. Per Assy Ri oo c. The output of dtron half-wave rectifier M13 is summed with the non-inverted signal at the input of Ml 4, with a weighting of 2: Sheet 2 gives tables of the coding on the input control lines from the Analog Interface. Datrln T1 and T2 are of toroidal construction mounted one on top of the other and bolted to the rear panel.

DATRON Digital Multimeter | eBay

Check display is For additional information, see the Global Shipping Programme terms and conditions – opens in a new window or tab. Additionally, at this time, the level 1 to level 2 transfer is repeated and the measurement circuits again updated to allow for commands received while the conversion is in progress.

Then on each Ohms range just a ‘Zero’ and ‘Gain’ calibration is required. The resultant impedance presented at the input terminals is a resistance of 1ML2, shunted by pF.

Thus the input current correction is floated on the bootstrap supply, tracking the input signal is divided by R84 to R and R to null the bias current of the preamplifier. For the purpose of explanation the same symbols are used, regardless of whether the switching is accomplished electronically F.

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Turn rear panel key switch to RUN. This is executed by clocking the ‘F. Check display is lOO. It should only be used when a full calibration i. The two ‘Zero’ calibrat- ions are included to overcome a possible zero difference with the polarity setting of the DC calibration source. Connect a shorting link between TP1 and TP3.

Check that display can be calibrated to lOO. A flowchart for the routine is given in Fig. M32 is the high inpedance buffer which tracks the inverting input of the preamplifier. Datrom L2 to give a stable -H. Guard is carried via the cable screens, thus guarding the signals during transfer. On each range a ‘Zero’ and ‘Gain’ calibration is required for each polarity of input. A simplified diagram of this arrangement is shown in Fig.

This voltage combined with the effect of the voltage 1061aa due to the DC Isolator being in Test 1061x 3. Filter components R and C90 eliminate the effects of current ‘kickback’ from M21 to the main signal path. Q31 is ‘closed’ from M causing a signal of 0. Turn rear panel keyswitch to RUN mode. Once this transfer of data is complete the RAM be- comes deselected, the buffers return to their third state inhibiting the data bus to the RAM and connects the ‘A’ inputs of M9 to the address lines of the RAM.

DATRON 1061 Digital Multimeter

A microprocessor MPU together with 16k bytes of memory controls the communication between the front panel, digital interface, display drivers. Apply IV, 50kHz and adjust C84 for a display reading of 1. Q6 and Q7 drive the clock output at voltage levels demanded by the processor OV and -t5V.

Then after recording the TLH voltage, refer to Fig. Connect Lo to Ohms Guard. For additional information, see the Global Shipping Programme terms and conditions – opens in a new window or tab This amount includes applicable customs duties, taxes, brokerage and other fees.

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The ID lines are set to the appropriate pattern and the information is clocked on to M13 and M14 by a delayed low to high edge from Mloriginating from I A0 going low.

DATRON A Digital Mulitmeter | eBay

This part of the procedure must be performed with the high frequency compensation voltage, at Jl-ll. Apply —1 volt d. The DC Isolator includes the preamplifier, range scaling circuits and bootstrapped supplies. An example of calibration with the Bus is given in the table below.

Datrln AC set-up procedure is now complete.

Ml Ratio assembly from M Data is extracted from the counters in three bytes controlled by the A1 and AO lines of the processor address bus with the count er output buffers, M24 and M25 being enabled by XADDT, datrob decoded processor address. In REF 2 the offset reduces by a factor of 16 giving the null reference point.

Repeat 17 and 18 until the 50kHz and kHz readings are separated by less than 20 digits. Q31 is ‘closed’ from M5 – 13 causing a signal of 0. M19 and M20 are backed up by a battery to privide the non-volatile ‘Calib- ration’ and ‘Zero’ memory. This occurs when memory locations starting at and its images are selected. The resulting voltage output dtaron the DC Isolator is applied to the A-D converter, measured and compared to the stored value.

REF 1 is ended when a 10661a detector pulse is detected and latched on to M Thus there is no voltage across Rz and consequently no current in Rz.